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ics for consumer electronics src-scan rate converter sda 9255 data sheet 1998-02-01
edition 1998-02-01 this edition was realized using the software system framemaker a published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 8.2.98. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements compo- nents may contain dangerous substanc- es. for information on the types in ques- tion please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc man- ufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support de- vices or systems must be expressly authorized for such purpose! critical components 1 of the semiconduc- tor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
ics for consumer electronics scan rate converter sda 9255 data sheet 1998-02-01
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. recommended operating conditions under this conditions the functions given in the circuit description are fulfilled. nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. if not stated otherwise, nominal values will apply at t a = 25c and the nominal supply voltage. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. edition 1998-02-01 published by siemens ag, semiconductor group copyright ? siemens ag 1997. all rights reserved. terms of delivery and right to change design reserved. sda 9255 revision histor y : current version: 1998-02-01 previous version: 1997-07-01 pa g e ( in previous version ) pa g e ( in current version ) sub j ects ( ma j or chan g es since last revision ) definition of n.c. pins
sda 9255 table of contents page semiconductor group 3 1998-02-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 input data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 output data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 input timing and parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 delay of vertical input synchronization signal . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 number of active lines of an input field . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 number of not active lines of an input field . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.4 not active pixels of input field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 output timing and parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 number of not active lines of output field . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 number of not active pixels of output field . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.3 vout, hout and href signal length . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.4 output synchronization raster and interlaced output signal . . . . . . . . . . . 16 2.5 motion adaptive temporal noise reduction . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 digital vertical zooming and panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7.1 i 2 c-bus slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7.2 i 2 c-bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7.3 i 2 c-bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7.4 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2 characteristics (assuming recommended operating conditions) . . . . 34 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 input timing of the sda 9255 (hsinp = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 output timing of the sda 9255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 internal vertical synchronization signal (vsinp = 0) . . . . . . . . . . . . . . . . . 37 5.4 example for not active input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.5 example for not active output register . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6 example for not active output pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.7 timing for hout signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.8 timing for vout signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.9 timing for href signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
sda 9255 table of contents page semiconductor group 4 1998-02-01 5.10 example for interlaced signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.11 i 2 c-bus timing start/stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.12 i 2 c-bus timing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.13 timing diagram clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
p-mqfp-64-1 semiconductor group 5 1998-02-01 src-scan rate converter sda 9255 cmos type ordering code package sda 9255 Q67101-H5190 p-mqfp-64-1 1 overview 1.1 features ? 100/120 hz interlaced scan conversion ? data format 4:1:1 ? on chip field memory ? digital vertical zooming ? digital vertical panning ? motion adaptive temporal noise reduction, field based ? still field ? color difference input data representation 2s complement or unsigned ? color difference output data representation 2s complement or unsigned ? sync generation for backend ic ? i 2 c-bus control (400 khz) ? p-mqfp-64 package ? 5 v 5 % supply voltage 1.2 general description the sda 9255 is a new component of the siemens megavision ? ic set. the sda 9255 comprises some of the functionalities of the megavision ? ics sda 9220 (memory sync controller) and sda 9254 (triple tv-sam plus noise reduction) and can therefore be used as a low cost digital featurebox.
sda 9255 semiconductor group 6 1998-02-01 1.3 pin configuration figure 1 uep10014 1 48 ss v 32 49 yin7 ss v yout5 testi0 sda 9255 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ss v test ll2clk testo7 testo8 testo9 dd v ss v ll2clk interlaced hout vout href yout7 yout6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 yout4 yout3 yout2 yout1 yout0 ss v dd v uvout7 uvout6 uvout5 uvout4 testo0 testo1 testo2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 testo6 testo5 testo4 testo3 reset syncen v ss dd v ss v hin vin sda scl testin testen 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 testi1 testi2 testi3 uvin4 uvin5 uvin7 uvin6 v dd yin0 yin1 yin2 yin3 yin4 yin5 yin6
sda 9255 semiconductor group 7 1998-02-01 1.4 pin description s: supply, i: input, o: output, ttl: digital (ttl) pin no. name type description 2,8,24,26,41,55, 57 v ss s supply voltage ( v ss =0v) 9,25,40,56 v dd s supply voltage ( v dd =5v) 42,...,49 yin0 ... 7 i/ttl data input y ( see data format ) 36,...,39 uvin4 ... 7 i/ttl data input uv ( see data format ) 30 syncen i/ttl synchronization enable input 31 reset i/ttl system reset. the reset input is low active. in order to ensure correct operation a " power on reset " must be performed. the reset pulse must have a minimum duration of two clock periods of the system clock (ll2clk). 23 hin i/ttl h-sync input 22 vin i/ttl v-sync input 21 sda i/o i 2 c-bus data line 20 scl i i 2 c-bus clock line 19 testin i/ttl test input, connect to v ss for normal operation 18 testen i/ttl test enable input, connect to v ss for normal operation 13,...,10 uvout4 ... 7 o/ttl data output uv ( see data format ) 7,...,3,1,64,63 yout0 ... 7 o/ttl data output y ( see data format ) 62 href o/ttl horizontal active video output 61 vout o/ttl v-sync output 60 hout o/ttl h-sync output 59 interlaced o/ttl interlace signal for ac coupled vertical deflection 58,51 ll2clk i/ttl system clock 50 test i/ttl test input, connect to v ss for normal operation 27,28,29, 52,53,54 testo 4...9 o do not connect, pins have to be left open 14,15,16,17 testo 0...3 o not used output stages, do not connect to any other driver, v ss or v dd ; pins can be left open 32,33,34,35 testi 0...3 i input stages (internal pull-down); pins can be left open
sda 9255 semiconductor group 8 1998-02-01 1.5 block diagram figure 2 memory controller field memory vertical zooming panning upconversion form 2 c-bus interface i noise reduction reform sync signal generator uvin yin interlaced hout vout href yout uvout sda scl dd vv ss hin vin syncen ueb10013
sda 9255 semiconductor group 9 1998-02-01 2 system description the device generates at its output an opportune sequence of 100/120 hz fields ( aabb ) [50/60 hz frames ( ab )] derived by processing the field a or b which is stored in one internal field memory. the fields can be noise reduced and vertically zoomed. additionally the device generates a vertical sync pulse, a horizontal sync pulse and a horizontal reference signal (horizontal active video output) in phase with the output data. furthermore an interlace signal for ac coupled vertical deflection is available. 2.1 input data formats the sda 9255 accepts at the input side the following input format (relations of y : (b-y) : (r-y) : 4 : 1 : 1). the representation of the samples of the chrominance signal is programmable as positive dual code (unsigned) or two's complement code (twoin, twoout, subaddress 00 h , see description of i 2 c bus ). x ab : x: signal component, a: sample number, b: bit number the amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 27 mhz. data pin sda 9255 yin7 y 07 y 17 y 27 y 37 yin6 y 06 y 16 y 26 y 36 yin5 y 05 y 15 y 25 y 35 yin4 y 04 y 14 y 24 y 34 yin3 y 03 y 13 y 23 y 33 yin2 y 02 y 12 y 22 y 32 yin1 y 01 y 11 y 21 y 31 yin0 y 00 y 10 y 20 y 30 uvin7 u 07 u 05 u 03 u 01 uvin6 u 06 u 04 u 02 u 00 uvin5 v 07 v 05 v 03 v 01 uvin4 v 06 v 04 v 02 v 00
sda 9255 semiconductor group 10 1998-02-01 2.2 output data formats x ab : x: signal component, a: sample number, b: bit number 2.3 input timing and parameter the sda 9255 has five input signals: the sda 9255 includes a v-sync delay block.this is implemented to make sure that the field identification is working correctly. this is briefly described below. the phase relation of the incoming horizontal synchronization signal (hin) and the incoming data for hsinp = 0 and vsinp = 0 is shown in figure 7 ( see chapter 5.1, input timing of the sda 9255 (hsinp = 0) ). the sda 9255 needs the synchronization enable input (syncen) which is used to gate hin and vin. this is implemented for frontends which are working with 13.5 mhz and a large output delay time for h-sync and data pin yout7 y 07 y 17 y 27 y 37 yout6 y 06 y 16 y 26 y 36 yout5 y 05 y 15 y 25 y 35 yout4 y 04 y 14 y 24 y 34 yout3 y 03 y 13 y 23 y 33 yout2 y 02 y 12 y 22 y 32 yout1 y 01 y 11 y 21 y 31 yout0 y 00 y 10 y 20 y 30 uvout7 u 07 u 05 u 03 u 01 uvout6 u 06 u 04 u 02 u 00 uvout5 v 07 v 05 v 03 v 01 uvout4 v 06 v 04 v 02 v 00 hin pin 23 horizontal synchronization signal - low or high active vin pin 22 vertical synchronization signal - low or high active syncen pin 30 enable signal for hin and vin signal, low active yin0 ... 7 pin 42, 43, 44, 45, 46, 47 ,48, 49 luminance input uvin4 ... 7 pin 36, 37, 38, 39 chrominance input
sda 9255 semiconductor group 11 1998-02-01 v-sync (e.g. intermetall vpc3200a, output delay: 35 ns). for this application the half system clock (13.5 mhz) from the frontend should be provided at this pin. in case the frontend is working at 27.0 mhz with sync signals whose delay time are smaller than 25 ns, this input can be set to low level (syncen = v ss ) (e.g. siemens sda 9257, sda 9206, output delay: 25 ns). thus the falling edge of hin signal is detected when the syncen input is low. the incoming hin (and vin) is sampled with the system clock (ll2clk = 27.0 mhz). the register value hsdly and mcnapip (subaddress 0b h and 0c h , see description of i 2 c bus ) have to be adjusted in the way that the distance from the falling edge of the hin to the first active pixel is correct. the half, quarter and eighth system clock is also shown in this diagram. they are generated inside the sda 9255. the half system clock (ll_clk = 13.5 mhz) is used to sample the incoming yuv data and run some blocks inside the sda 9255. the quarter system clock (lh_clk = 6.75 mhz) is used to run some blocks inside the sda 9255. the eighth system clock (lq_clk = 3.375 mhz) is used to synchronize the 4:1:1 input data stream. the setting of the register hsdly and mcnapip is explained in chapter 1 . the sda 9255 has a fixed number of active pixels per input line. it is fixed to 720 luminance pixels and 180 chrominance pixels. 2.3.1 delay of vertical input synchronization signal in order to have always the same raster of the vertical and horizontal synchronization signal inside the sda 9255 it is possible to shift the v-sync signal. the subaddress 09 h of the sda 9255 (vsdly, see description of i 2 c bus ) controls the shift of the v-sync. the user has to know the input sync raster and then the user can adjust the vsdly register value in the way that the field identify circuit inside the sda 9255 can work properly. the adjustment of the v-sync can be done in steps of 32 clock periods (ll2clk). thus the delay is also dependent on the system clock frequency. the formula to calculate the delay is shown below. delay (vin to vs_int) = (vsdly * 32 + 7 ... 11) * t ll2clk where: vin: incoming v-sync at pin 22; vsdly: is the register value vs_int: internal v-sync t ll2clk : system clock period (e.g 1/27.0 mhz = 37.04 ns) the initial delay (7 ... 11 system clocks) is caused by flip-flops at the input. this delay is not a fixed number, because a quarter of the system clock (lh_clk) is used to set the delay. the phase of the lh_clk is dependent on the reset and the syncen ( see figure 7 ). an example shows figure 9 ( see chapter 5.3, internal vertical synchronization signal (vsinp = 0) ). in this example the falling edge of the vin signal of field a is at 35 m s and the falling edge of the vs_int signal is at 16 m s (both signals are related to the falling
sda 9255 semiconductor group 12 1998-02-01 edge of the previous hs_int, compare chapter 1 ). thus the sampling points of the field identify circuit (marked in the diagram with ?a and ?b) have uniform distances to the falling edge of the vs_int. the falling edge of the vin signal of field b is at 3 m s and the falling edge of the vs_int signal is at 48 m s (related to the falling edge of the previous hin). here the sampling points have also uniform distances to the falling edge of the vs_int signal. the user should adjust this value carefully. dependent on the input mode of the frontend circuit the integration time of the v-sync can change. for non-standard signals, for instance, a shorter integration time may be chosen. the internal v-sync (vs_int) must have the falling edge at line 2 for field a. all the other settings (nalip ...) are dependent on this internal v-sync. the default setting of the vsdly is 3a h . this corresponds to a delay of about 69 m s (58(=3a h ) * 32 * 37 ns), which suits for the clock sync generator sda 9257 and sda 9206. 2.3.2 number of active lines of an input field the subaddress 0a h (al, see description of i 2 cbus ) is used to adjust the number of active lines per input and output field. it is independent of the mode10050 in subaddress 00 h . the register value al has to be chosen in the following way: 2.3.3 number of not active lines of an input field due to the fact that the sda 9255 stores only the active field in the field memory, it requires the information of the start of the active field and the active line. a not-active- line counter (nalip, subaddress 0b h , see description of i 2 c bus ) starts counting the incoming h-syncs when it detects a falling edge of the vs_int signal. if vs_int is adjusted as recommended in the explanation of subaddress 09 h then the calculation of the nalip value can be done in the following way: nalip = first active line of field a C 5 (e.g. 23 C 5 = 18) in figure 10 ( see chapter 5.4, example for not active input register ) an example for nalip = 18 is shown. as you can see for field a 21 h-syncs are counted and for field b 22 h-syncs are counted. if nalip is set to '0' line 5 is the first active line of field a and line 318 the first active line of field b (318 C 5 = 313). the difference between first active line of field b and field a should be: d = (no.lines per frame div 2) + 1; e.g. d =625div2+1=313 al number of lines per field 2 C 2 ------------------------------------------------------------------------- - e.g. 288 2 C 2 ------------------ - 143 = ? ?? ; =
sda 9255 semiconductor group 13 1998-02-01 2.3.4 not active pixels of input field in the sda 9255 an h-sync delay circuit is implemented. the output of this block is the hs_int. the distance of the incoming h-sync (hin, falling edge for hsinp = 0) and the active data is adjustable by the hsdly register value and the mcnapip register value (subaddress 0b h and 0c h , see description of i 2 cbus ). with the hsdly register the delay of the external (hin) to the internal h-sync (hs_int) is adjustable. delay (hin to hs_int) = (hsdly * 64 + 4) * t ll2clk this internal h-sync (hs_int) is fed to the memory control unit. the mcnapip (memory controller not active pixel at input) is used to adjust the distance to the active line in steps of one system clock period. so the mcnapip is used to set the phase of the internal generated clocks ll_clk, lh_clk and lq_clk. delay (hs_int to active data) = (mcnapip + 61) * t ll2clk the total distance of the falling edge of the incoming h-sync (hin, falling edge for hsinp = 0) to the active data of the line is: delay (hin to active data) = (hsdly * 64 + mcnapip + 65) * t ll2clk in the formula above you can see that the first active pixel occurs 65 system clocks after the falling edge of the hin signal, if hsdly and mcnapip are set to zero. in the figure 7 ( see chapter 5.1, input timing of the sda 9255 (hsinp = 0) ) the input timing of the sda 9255 is shown. the luminance and chrominance data are coming with half the system clock speed (e.g. 13.5 mhz). the sda 9255 accepts the yin data every second edge of the ll2clk clock; in the sda 9255 the luminance and chrominance data are sampled with the rising edge of the internal ll_clk, which is half the system clock (e.g. 13.5 mhz). at the position of the first active pixel the phase of the half system clock (ll_clk = 13.5 mhz), the quarter system clock (lh_clk = 6.75 mhz) and the eighth system clock (lh_clk = 3.375 mhz) is always as shown in the diagram. the ll_clk is used for sampling the incoming data. the lq_clk is used to synchronize the 4:1:1 data stream.
sda 9255 semiconductor group 14 1998-02-01 2.4 output timing and parameter the sda 9255 has six output signals: there are different modes of output synchronization raster possible. the data output signal of the sda 9255 (yout, uvout and href) are fed to the digital-to-analog converter. the timing of the output signals is given in figure 8 ( see chapter 5.2, output timing of the sda 9255 ). 2.4.1 number of not active lines of output field the register values nalop and napop are used to set the position of the active output field on the screen. to do this the register value to align the not active lines (nalop, subaddress 0d h , see description of i 2 cbus ) and the register value to align the not active pixels (napop, subaddress 0e h , see description of i 2 cbus ) for the output signal are available. to change the vertical position of the picture on the screen the nalop register can be utilized. the nalop register (not active lines for output) is used to adjust the number of not active output lines in steps of two lines in case of 100/120 hz interlaced and in steps of four lines in case of 50/60 hz proscan. to calculate the first active output line the following formula can be used: for mode10050 = 0 ==> 100/120 hz interlaced: faopl = nalop * 2+3 for mode10050 = 1 ==> 50/60 hz proscan: faopl = nalop * 4+5 where faopl: the first active output line nal_op: register value the maximum value for the first active line is 65 for 100/120 hz and 129 for 50/60 hz. in figure 11 ( see chapter 5.5, example for not active output register ) an example for the setting of the nalop register is shown. the synchronization output (hout, hout pin 60 horizontal synchronization signal - high active vout pin 61 vertical synchronization signal - high active href pin 62 horizontal active video output interlaced pin 59 interlace signal yout0 ... 7 pin 7, 6, 5, 4, 3, 1, 64, 63 luminance output uvout4 ... 7 pin 13, 12, 11, 10 chrominance output
sda 9255 semiconductor group 15 1998-02-01 vout, href) signals are high active. in the example the register value is 10 and the mode is '0' (100/120 hz/interlaced). faopl = nalop * 2+3=10 * 2+3=23 so line 23 is the first active output line. for proper operation the number of not active lines at output side plus the number of active lines have to be smaller than the total number of lines. the following formula should be true. nalop * 2+al * 2+3 (no. of lines per frame) div 2 (e.g. 312) where al: register value nalop: register value 2.4.2 number of not active pixels of output field to change the horizontal position of the picture on the screen the napop register value can be utilized. the not active pixels for output register ( napop ) is used to adjust the number of not active output pixels of a line. the register value is multiplied by '4' and has an initial value of 9 ... 12 (hsodly = 0), depending on the mcnapip setting (subaddress 0b h and 0c h , see description of i 2 cbus ). faopp = napop * 4 + 9 ... 12 C hsodly = 0 faopp = napop * 4 + (- 163) ... (- 160) ; hsodly = 1 is equal to : faopp = napop * 4 + 9 ... 12 C 172 * hsodly where faopp: the first active output pixel after rising edge of hout napop: register value hsodly: register value the time from the rising edge of the hout signal to the first active output pixel can be calculated in the following way: t napop =( napop * 4 + 9 ... 12 ) * t ll2clk ;hsodly=0 t napop =(napop * 4 + (- 163) ... (-160)) * t ll2clk ;hsodly=1 where t napop : time from rising edge of hout to first active output pixel t ll2clk : system clock period (e.g. 1/27 mhz) figure 12 ( see chapter 5.6, example for not active output pixels ) shows the effect of the register napop.
sda 9255 semiconductor group 16 1998-02-01 2.4.3 vout, hout and href signal length the length of the output synchronization signals (hout, vout) is fixed. the hout signal is active high with a length of 32 system clocks (27.0 mhz) which corresponds to a length of 1.185 m s. the vout signal is also active high with a length of 2 output lines. so in case of pal b/g the active high period of the vout lasts for 64 m s ( see figure 13, timing for hout signal and figure 14, timing for vout signal ). the hout signal of the sda 9255 can be delayed by a fixed value of 172 system clocks (27.0 mhz) by setting the hsodly bit of subaddress 0f h to 1( see description of i 2 cbus ). the number of active pixels per line is constant 720 pixels. the href output signal (pin 62) indicates the active part of the output lines. the length is also constant (720 system clocks). during the vertical and horizontal blanking period this signal is low. the timing is shown in figure 15 ( see chapter 5.9, timing for href signal ). the chrominance output format is like the output format as described in chapter 1 . 2.4.4 output synchronization raster and interlaced output signal the output synchronization and data raster in 100/120 hz mode can be set by the modesync register value (subaddress 01 h , see description of i 2 cbus ). in case of mode10050 = 1 (50/60 hz pro-scan mode) this register value has no effect. the interlaced signal interlaced (pin 59) is a control signal which may be used to control an ac coupled vertical deflection unit. if the modesync register value (subaddress 01 h , see description of i 2 cbus ) is set to aabb mode, where field 2 and 3 have to be shifted down (modesync = 10). for this the interlaced register intl (subaddress 0d h and 0e h , see description of i 2 cbus ) must be set to 0110. in figure 16 ( see chapter 5.10, example for interlaced signal ) an example for the intl register value is shown. bit zero defines the output for the first field (field a); bit one defines the output for the second field (field a); bit two defines the output of the third field (field b); bit three defines the output of the fourth field (field b). so if the bit is set to zero then the output is low and if the bit is set to one then the output is high. for dc coupled vertical deflection the interlaced signal is not required.
sda 9255 semiconductor group 17 1998-02-01 2.5 motion adaptive temporal noise reduction figure 3 block diagram of noise reduction the diagram above shows a block diagram of the motion adaptive noise reduction. the noise reduction in the luminance path has the same structure as the noise reduction in the chrominance path. subaddresses 02 h and 03 h (nrkf0, nrkf1, nrkf2, nrkf3, see description of i 2 cbus ) are used to align the filter coefficients of the noise reduction iir filter. four different k-factors nrkf0 ... 3 can be modified which are fed to the multiplier of the iir filter. depending on the output of the motion detection for noise reduction (mdfornr) the corresponding k-factor nrkf0 ... 3 is used for the iir filter ( see the table below ). ueb10015 lut address mdfornr nrkf0 nrkf1 nrkf2 nrkf3 + * - yin/uvin field memory - + + k-factor
sda 9255 semiconductor group 18 1998-02-01 table 1 mdfornr and corresponding k-factor for nrkf0 ... 3 values between 0 and 7 can be chosen. the following table shows the theoretical amount of noise reduction dependent on the applied k-factor. table 2 filter coefficients dependent on the k-factor the subaddresses 04 h , 05 h and 06 h (mdnrth0, mdnrth1, mdnrth2, see description of i 2 cbus ) are used to align the motion detection for noise reduction (mdfornr). the sensitivity of the motion detection is influenced by changing the threshold levels of the motion values. a rough block diagram of the motion detection for noise reduction is shown below. mdfornr k-factor mode 0 nrkf0 still 1 nrkf1 quasi still 2 nrkf2 quasi motion 3 nrkf3 motion k-factor amount of nr 00 db 1 1.1 db 2 2.2 db 3 3.4 db 4 4.8 db 5 6.4 db 6 8.5 db 7 11.8 db
sda 9255 semiconductor group 19 1998-02-01 figure 4 block diagram of motion detection for noise reduction the input signals for the motion detection for noise reduction are the just incoming luminance signal (yin) and the already noise reduced luminance signal on one field delay (dyin). both signals are fed to a subtractor, followed by a low pass filter. this filter can be bypassed by setting the nrhf bit ( see description subaddress 08 h , bit 0 ) to 0. the absolute value is calculated and given to a limiter block. the output signal is fed to the threshold block, where the value is quantized by using the 3 threshold values mdnrth0, mdnrth1 and mdnrth2. the quantization characteristic of the threshold block is shown by the following table and diagram. table 3 quantization table of mdfornr input value output mode 0 ... (th0 C 1) 0 still th0 ... (th1 C 1) 1 quasi still th1 ... (th2 C 1) 2 quasi motion th2 ... 31 3 motion + - noise reduction memory field yin dyin filter low pass mux 1 0 abs limiter threshold mux 0 1 mdnrth2 mdnrth1 mdnrth0 mdfornr nrhf snr fnr ueb10016
sda 9255 semiconductor group 20 1998-02-01 figure 5 quantization characteristic of mdfornr the following table shows an example for noise reduction settings. these five settings could be implemented and the customer can choose, which he prefers. for example, to have a subjective impression of medium noise reduction of the picture, you have to set the k-factors: nrkf0 = 4, nrkf1 = 3, nrkf2 = 2, nrkf3 = 0 and mdnrth0 = 4, mdnrth1 = 8 and mdnrth2 = 12. table 4 example for noise reduction settings amount of noise reduction parameter no slightly medium strong heavy nrkf003477 nrkf102345 nrkf201223 nrkf300001 mdnrth0 dont care 2444 mdnrth1 dont care 6 8 10 10 mdnrth2 dont care 10 12 14 16 ueb10017 0 1 2 3 mdnrth0 mdnrth1 mdnrth2 ~ ~ 0 31
sda 9255 semiconductor group 21 1998-02-01 2.6 digital vertical zooming and panning the user can choose 17 different zoom factors and 37 pan factors. every zoom factor can be used without considering other register values, but on the other hand the pan factor is very much dependent on the zoom factor. so be careful in choosing the pan factor. in the following table the zoom factor (subaddress 0f h , see description of i 2 cbus ) and the corresponding visual zoom of the input field is shown. in the third column the required number of input lines is shown, when the number of displayed output lines is 288. the fourth column shows the allowed value pan value (subaddress 10 h , see description of i 2 cbus ) and the last column the pan register value for vertical centre position. table 5 table of zoom factors and panning factors dependent on the zoom factor the sda 9255 requires a certain number of input lines of a field. zoom visual zoom noipl (noopl = 288) panning range pan centre panning pan 16 1 288 0 0 15 1.03 279 0 ... 2 1 14 1.06 270 0 ... 4 2 13 1.10 261 0 ... 6 3 12 1.14 252 0 ... 9 4 11 1.18 243 0 ... 11 5 10 1.23 234 0 ... 13 6 9 1.28 225 0 ... 15 7 8 1.33 216 0 ... 18 8 7 1.39 207 0 ... 20 10 6 1.45 198 0 ... 22 11 5 1.52 189 0 ... 24 12 4 1.6 180 0 ... 27 13 3 1.68 171 0 ... 29 14 2 1.77 162 0 ... 31 15 1 1.88 153 0 ... 33 17 0 2.0 144 0 ... 36 18
sda 9255 semiconductor group 22 1998-02-01 where noipl: number of required input lines noopl: number of generated output lines (al * 2) + 2 zoom: register value (0 ... 16) in the third column of the table above the required number of input lines is shown, if the generated number of output lines is 288 (al = 143). in the last row you can see that for the visual zoom factor of 2 half the number of input lines is necessary, which is of course obvious. as mentioned before, only zoom factors between '0' and '16' are allowed. if factors bigger than 16 are chosen, they are set to '16'. panning is possible in steps of 4 input lines. so the first active input line which is used to generate the first active output line can be calculated in the following way: faipl = pan * 4+1 where faipl: first active input line to generate the first active output line pan: register value with pan = 0 the first active input line is line 1, as expected. in case of pan = 1 the first active input line is line 5, etc. so the allowed register value for pan can be calculated from the last column of the table above. in this example with 288 active lines and, for instance, zoom factor of '15', the maximum pan factor is '2'. pan = '3' is permitted which can be seen by this calculation: 3 * 4 + 279 = 291. the required number of input lines plus the panning lines is larger than the actual number of input lines (288). a formula to calculate the maximum pan factor is shown below. after some rearranging of the formula we get this simple formula to calculate the maximum register value of the pan factor. where noipl: number of required input lines noopl: number of generated output lines (al * 2) + 2 noipl noopl zoom 2 32 + 64 ----------------------------------------- = pan int noopl noipl C 4 -------------------------------------------- - ? ? ? pan int noopl 8 -------------------- - 16 zoom C 16 ------------------------------- ? ? ?
sda 9255 semiconductor group 23 1998-02-01 zoom: register value (0 ... 16) pan: register value (0 ... 63) in the fourth column of table 5 the panning range is shown for noopl = 288. if the pan factor is larger than specified in the previous equation, the last input line is used for interpolation of the remaining lines. on the screen the last line is repeated. 2.7 i 2 c bus 2.7.1 i 2 c-bus slave address 2.7.2 i 2 c-bus format the sda 9255 i 2 c-bus interface acts as a slave receiver and a slave transmitter and provides three different access modes (write, read, continuous read). all modes run with a subaddress auto increment. the interface supports the normal 100 khz transmission speed as well as the high speed 400 khz transmission. write: s: start condition a: acknowledge p: stop condition na: not acknowledge read: continuous read: the transmitted data are internally stored in registers. the master has to write a dont care byte to the subaddress ff h (store command) to make the register values available for the sda 9255. to have a defined time step, where the data will be available, the data are made valid with the incoming v-sync or with the next sync_st pulse, which is an internal signal and indicates the start of a new output cycle of either four fields in 100/ 120 hz interlaced mode or two frames in 50/60 hz proscan mode. the subaddresses, where the data are made valid with the v-sync (every 20 ms) are indicated in the overview of the subaddresses with ?v, where the data are made valid with the 1011110 s10111100a su baddress a data byte a ***** ap s 1 0 1 1 1 1 0 0 a subaddress a s 1 0 1 1 1 1 0 1 a data byte a ***** data byte na p s 1 0 1 1 1 1 0 1 a data byte a ***** data byte na p write address: bc h read address: bd h
sda 9255 semiconductor group 24 1998-02-01 sync_st (every 40 ms) are indicated with ?s. the i 2 c-bus status bits of the sda 9255 (sub19 h , bit 7; sub1e h , bit 7) reflect the state of the register values. if these bits are read as 0 then the store command was sent, but the data arent made available yet. if these bits are 1 then the data were made valid and a new write or read cycle can start. the i 2 c-bus status bits have to be checked before writing or reading new data, otherwise data can be lost by overwriting. after switching on the ic, all bits of the sda 9255 are set to defined states. in particular: r/w: r-read register, w-write register, r/w-read and write register, take over: v-take over with v-sync, s-take over with sync_st subaddress default value r/w take over subaddress default value r/w take over 00 h 6f h r/w s 0c h a2 h r/w v 01 h 56 h r/w s 0d h 50 h r/w s 02 h 68 h r/w v 0e h 2c h r/w s 03 h 23 h r/w v 0f h 81 h r/w s 04 h 10 h r/w v 10 h 00 h r/w s 05 h 30 h r/w v 11 h ... 18 h not used r/w 06 h 50 h r/w v 19 h r 07 h not used r/w 1a h ... 1d h not used r/w 08 h 61 h r/w v 1e h r 09 h 74 h r/w v 1f h ... fe h not used r/w 0a h 8f h r/w v ff h w 0b h 94 h r/w v
sda 9255 semiconductor group 25 1998-02-01 2.7.3 i 2 c-bus commands x = dont care subadd. (hex.) data byte d7 d6 d5 d4 d3 d2 d1 d0 00 h mode10050 1 1 freeze twoin twoout tvmode1 tvmode0 01 h 01010 modesync1 modesync0 0 02 h nrkf02 nrkf01 nrkf00 nrkf12 nrkf11 nrkf10 x x 03 h nrkf22 nrkf21 nrkf20 nrkf32 nrkf31 nrkf30 hsinp vsinp 04 h mdnrth04 mdnrth03 mdnrth02 mdnrth01 mdnrth00 x x x 05 h mdnrth14 mdnrth13 mdnrth12 mdnrth11 mdnrth10 x x x 06 h mdnrth24 mdnrth23 mdnrth22 mdnrth21 mdnrth20 x x x 08 h snrfnr1fnr0xxxx nrhf 09 h vsdly6 vsdly5 vsdly4 vsdly3 vsdly2 vsdly1 vsdly0 x 0a h al7 al6 al5 al4 al3 al2 al1 al0 0b h nalip4 nalip3 nalip2 nalip1 nalip0 mcnapip6 mcnapip5 mcnapip4 0c h mcnapip3 mcnapip2 mcnapip1 mcnapip0 hsdly3 hsdly2 hsdly1 hsdly0 0d h nalop4 nalop3 nalop2 nalop1 nalop0 intl3 intl2 intl1 0e h napop6 napop5 napop4 napop3 napop2 napop1 napop0 intl0 0f h zoom4 zoom3 zoom2 zoom1 zoom0 x x hsodly 10 h pan5 pan4 pan3 pan2 pan1 pan0 x x 19 h vstatusxxxxxxx 1e h sstatusxxxxxxx ff h xxxxxxxx
sda 9255 semiconductor group 26 1998-02-01 2.7.4 detailed description subaddress 00 h bit name function d7 mode10050 output mode switch: 0: 100/120 hz (default value) 1: 50/60 hz d6 1: should be set to 1 d5 1: should be set to 1 d4 freeze still picture: 0: off (default value) 1: on d3 twoin chrominance input format: 0: unsigned input (0 ... 255) 1: 2s complement input (-128 ... 127) (default value) inside the sda 9255 the data are always processed as unsigned data d2 twoout chrominance output format: 0: unsigned output (0 ... 255) 1: 2s complement output (-128 ... 127) (default value) d1 ... d0 tvmode television system: 00: ntsc (1716) 01: automatic pal (n * 32) 10: automatic ntsc (n * 32+20) 11: pal (1728) (default value) the sda 9255 is designed for a line-locked system. therefore the number of system clock periods between two h-sync (hin) must be constant. in pal (1728) mode the number of system clocks (~27.0 mhz) per input line is assumed to be constant 1728. in case of ntsc (1716) mode the number of system clock periods is assumed to be constant 1716. in automatic mode (01 and 10) the number of system clock periods (~27.0 mhz) per incoming line is measured and used to calculate the outgoing line length. in automatic pal mode the number of system clock periods between two h-syncs must be n * 32 (n = 1, 2, ..., 54, ...). in automatic ntsc mode the number of system clock periods between two h-syncs must be n * 32 + 20 (n = 1, 2, ..., 53, ...).
sda 9255 semiconductor group 27 1998-02-01 subaddress 01 h bit name function d7 ... d3 should be set to 01010 d2 ... d1 modesync output synchronization mode: 00: reserved 01: aabb mode for ac coupled vertical deflection, no data shift 10: aabb mode for ac coupled vertical deflection, field 2 and 3 shift down 11: aabb mode for dc coupled vertical deflection (default value) d0 0: should be set to 0 subaddress 02 h bit name function d7 ... d5 nrkf0 noise reduction k-factor kf 0: 011: (default value) d4 ... d2 nrkf1 noise reduction k-factor kf 1: 010: (default value) d1 ... d0 xx
sda 9255 semiconductor group 28 1998-02-01 subaddress 03 h bit name function d7 ... d5 nrkf2 noise reduction k-factor kf 2: 001: (default value) d4 ... d2 nrkf3 noise reduction k-factor kf 3: 000: (default value) d1 hsinp h-sync input polarity: 0: low active 1: high active (default value) d0 vsinp v-sync input polarity: 0: low active 1: high active (default value) subaddress 04 h bit name function d7 ... d3 mdnrth0 noise reduction threshold 0: 00010: (default value) d2 ... d0 xxx subaddress 05 h bit name function d7 ... d3 mdnrth1 noise reduction threshold 1: 00110: (default value) d2 ... d0 xxx subaddress 06 h bit name function d7 ... d3 mdnrth2 noise reduction threshold 2: 01010: (default value) d2 ... d0 xxx
sda 9255 semiconductor group 29 1998-02-01 subaddress 08 h bit name function d7 snr switch for fixed value for motion detection for noise reduction 0: off (default value) 1: on d6 ... d5 fnr fixed value for motion detection for noise reduction 11: (default value) d4 ... d1 xxxx d0 nrhf switch for low pass filter for motion detection for noise reduction 0: off 1: on (default value) subaddress 09 h bit name function d7 ... d1 vsdly v-sync input delay (default value 3a h ) d0 x subaddress 0a h bit name function d7 ... d0 al (number of active input lines per field C 2) / 2 (default value 8f h ) subaddress 0b h bit name function d7 ... d3 nalip number of not active lines of input data (default value 12 h ) d2 ... d0 mcnapip6 ... 4 number of system clocks from internal hs_int to active input data, bit 6 to 4 (default value 4 h )
sda 9255 semiconductor group 30 1998-02-01 subaddress 0c h bit name function d7 ... d4 mcnapip3 ... 0 number of system clocks from internal hs_int to active input data, bit 3 to 0 (default value a h ) d3 ... d0 hsdly h-sync input delay (default value 2 h ) subaddress 0d h bit name function d7 ... d3 nalop number of active lines at output (default value a h ) d2 ... d0 intl3 ... 1 interlace output for field bit 3 to 1 (default value 0 h ) subaddress 0e h bit name function d7 ... d1 napop number of not active pixels at output (default value 16 h ) d0 intl0 interlace output for field bit 0 (default value 0 h ) subaddress 0f h bit name function d7 ... d3 zoom zooming factor (default value 10 h ) d2 ... d1 xx d0 hsodly delay of h-sync output (default value 1 h ) subaddress 10 h bit name function d7 ... d2 pan panning of the output picture (default value 0 h ) d1 ... d0 xx
sda 9255 semiconductor group 31 1998-02-01 subaddress 19 h bit name function d7 vstatus status bit for subaddresses, which will be made valid by v- sync d6 ... d0 xxxxxxx subaddress 1e h bit name function d7 sstatus status bit for subaddresses, which will be made valid by sync_st d6 ... d0 xxxxxxx subaddress ff h bit name function d7 ... d0 store command for all subaddresses, xxxxxxxx
sda 9255 semiconductor group 32 1998-02-01 3 absolute maximum ratings all voltages listed are referenced to ground (0 v, v ss ) except where noted. note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. parameter symbol limit values unit remark min. max. operating temperature t a 070c storage temperature -65 125 c junction temperature 125 c soldering temperature 260 c soldering time 10 s input voltage -0.3 v dd +0.3 v output voltage -0.3 v dd +0.3 v supply voltages v dd -0.3 6 v total power dissipation 1.2 w esd protection -2 2 kv mil std 883c method 3015.6, 100 pf, 1500 w latch-up protection -100 100 ma all inputs/outputs
sda 9255 semiconductor group 33 1998-02-01 3.1 recommended operating conditions parameter symbol limit values unit remark min. nom. max. supply voltages v dd 4.75 5 5.25 v ambient temperature t a 0 25 70 c all ttl inputs h-input voltage v ih 2.0 v dd v l-input voltage v il 0 0.8 v all ttl outputs h-output voltage v qh 2.4 v i qh = -2.0 ma l-output voltage v ql 0.4 v i ql =3.0ma input/output: sda l-output voltage v ql 0.5 v at i ql =max clock ttl input ll2clk clock frequency 1/t 27 mhz see figure 19 low time t wl 12 ns high time t wh 12 ns rise time t tlh 5ns fall time t thl 5ns i 2 c bus (all values are referred to min ( v ih ) and max ( v il )), f scl = 400 khz h-input voltage v ih 3 v dd v see figure 17 l-input voltage v il 0 1.5 v see figure 18 scl clock frequency f scl 0 400 khz inactive time before start of transmission t buf 1.3 m s set-up time start condition t su; sta 0.6 m s hold time start condition t hd; sta 0.6 m s scl low time t low 1.3 m s scl high time t high 0.6 m s set-up time data t su; dat 100 ns hold time data t hd; dat 0 m s
sda 9255 semiconductor group 34 1998-02-01 3.1 recommended operating conditions (contd) 3.2 characteristics (assuming recommended operating conditions) parameter symbol limit values unit remark min. nom. max. sda/scl rise times t r 300 ns sda/scl fall times t f 300 ns set-up time stop condition t su; sto 0.6 m s output valid from clock t aa 900 ns input filter spike suppression (sda and scl pins) t sp 50 ns l-output current i ql 3ma parameter symbol limit values unit remark min. max. average supply current i cc 200 ma all v dd pins, typ. 170 ma all digital inputs (including i/o inputs) input capacitance c i 10 pf input leakage current i i(l) -10 10 m a ttl inputs: yin, uvin (referred to ll2clk) set-up time t su 0ns input hold time t ih 25 ns ttl inputs: hin, vin, syncen (referred to ll2clk) set-up time t su 7ns input hold time t ih 6ns ttl outputs: yout, uvout, hout, vout, href, interlaced (referred to ll2clk) hold time t qh 6ns delay time t qd 25 ns c l =30pf
sda 9255 semiconductor group 35 1998-02-01 4 application information figure 6 3adc csg sda 9206 scan rate converted 9255 sda sda 9280 processor display yi ui vi cvbs/ sync yout uout vout hout, vout 12 yuv yuv 12 hin, vin 13.5 mhz 27.0 mhz href 27.0 mhz clk clk ues10018
sda 9255 semiconductor group 36 1998-02-01 5 waveforms 5.1 input timing of the sda 9255 (hsinp = 0) figure 7 uet10019 ll2clk hsin hs_int llclk lh_clk lq_clk d/yin y0 y1 y2 y3 y4 d/uvin c2 c0 c1 c3 c4 ll2clk t (hs_dly x 64 + 4) x (mc_nap_op + 61) x t ll2clk (hs_dly x 64 + mc_nap_ip + 65) x t ll2clk ~ ~ ~ ~ xxxx xxxx ih t t su t ih t su
sda 9255 semiconductor group 37 1998-02-01 5.2 output timing of the sda 9255 figure 8 5.3 internal vertical synchronization signal (vsinp = 0) figure 9 uet10020 ll2clk (napop x 4 + 9...12 - t ll2clk hout href uvout yout y0 y1 y2 y3 y716 y717 y719 y718 c716 c0 c1 c2 c3 c719 c718 c717 x hsodly x 172) default value 16 black default value 0 (128) uncoloured default value default value ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ uet10021 hs_int vin vs_int line 625 line 1 line 2 line 3 delay(vin to vs_int) a a b b a sample points of field ident field a delay(vin to vs_int) field b vs_int a b a line 313 vin hs_int line 314 b a line 316 line 315
sda 9255 semiconductor group 38 1998-02-01 5.4 example for not active input register figure 10 5.5 example for not active output register figure 11 uet10022 line 1 line 625 line 2 line 3 line 24 line 23* line 22 line 25 vs_int hn line 312 hn vs_int line 314 line 313 line 315 line 335 line 336* line 337 line 338 * : first active line of a field ~ ~ ~ ~ ) ) ) uet10023 line 1 vout hout line 2 line 3 line 21 line 22 line 23 line 24 href yout uvout default value 16 black default value 0 (2's complement) or 128 (unsigned) uncoloured first active output line ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
sda 9255 semiconductor group 39 1998-02-01 5.6 example for not active output pixels figure 12 5.7 timing for hout signal figure 13 uet10024 ll2clk hout yout uvout y0 y1 y2 y3 y4 c3 c1 c0 c2 c4 (napop x 4 + 9...12 - hsodly x 172) x ll2clk t href c5 y5 qd t qh t default value 16 black default value 0 (128) uncoloured ~ ~ uet10025 ll2clk hout 32 x ll2clk t ~ ~ ~ ~
sda 9255 semiconductor group 40 1998-02-01 5.8 timing for vout signal figure 14 5.9 timing for href signal figure 15 uet10026 hout vout 2 x hout t t hout uet10027 ll2clk href yout uvout y0 y1 y2 y3 y4 y713 y714 y715 y716 y717 y718 y719 c718 c3 c1 c0 c2 c714 c4 c713 c716 c715 c717 c719 16 0 (128) 0 (128) 16 720 x ll2clk t ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
sda 9255 semiconductor group 41 1998-02-01 5.10 example for interlaced signal figure 16 5.11 i 2 c-bus timing start/stop figure 17 uet10028 field a field a field b field b field a vout yuvout interlaced intl1 intl2 intl0 intl3 intl0 uet10029 hd:sta t su:sta t su:sto t scl sda start stop v hys ~ ~ ~ ~ ~ ~
sda 9255 semiconductor group 42 1998-02-01 5.12 i 2 c-bus timing data figure 18 5.13 timing diagram clock figure 19 uet10030 low t high t t low t f r t t su:sta hd:sta t hd:dat t su:dat t t su:sto t aa aa t scl sda sda in out sp t buf t uet10031 wh t thl t t wl t tlh t ih v il v ll2clk
sda 9255 semiconductor group 43 1998-02-01 6 package outlines figure 20 gpm05250 17.2 14 0.8 0.3 +0.15 12 0.1 0.25 min +0.1 2 2.45 max 0.88 0.15 1) 1 64 0.6 x 45? index marking does not include plastic or metal protrusions of 0.25 max. per side a-b 0.2 h d 4x a-b 0.2 d 64x a d c 0.2 64x d a-b m c 1) 14 17.2 -0.05 h 7? max -0.02 +0.08 0.15 b 1) p-mqfp-64-1 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. smd = surface mounted device dimensions in mm

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